Column-Parallel Circuits with Digital Correlated Multiple Sampling for Low Noise CMOS Image Sensors

This paper presents a low noise CMOS image sensor using column-parallel high-gain signal readout and digital correlated multiple sampling (CMS). The sensor used is a conventional 4T active pixel architecture with a pinned-photodiode as detector. The test sensor has been fabricated in a 0.18μm CMOS image sensor process from TSMC. The random noise from the pixel readout chain is reduced in two stages, first using a high gain column parallel amplifier and second by using the digital CMS technique. The dark random noise measurement results show that the proposed column-parallel circuit with digital CMS technique is able to achieve 127 μVrms (2.8 e) input referred noise. The significant reduction in the sensor read noise enhances the sensor’s SNR with 10.4 dB. Such sensors are very attractive for low light imaging applications which demand high SNR values. DESIGN AND OPERATION PRINCIPLE: Fig. 1 shows the simplified schematic diagram of the 4T pixel with a pinned-photodiode and the proposed column readout circuits, including a gain amplifier and a single slope A/D converter (SS-ADC). The use of the column gain amplifier can reduce the noise by amplifying the signal which will narrow the bandwidth due to the conservation product of gain and bandwidth, before the rest read noise is added. The gain here is defined by the capacitance ratio of Cin/Cfb, where Cin is the input capacitor, and Cfb is the feedback capacitor of column gain amplifier, respectively. The output of the column gain amplifier is connected to the column SS-ADC using an auto-zero capacitor Caz. The column SS-ADC consists of a comparator, driven by a ramp voltage and a bit-wise inversion (BWI) counter [1]. The BWI counter shows 32% reduction in power consumption and 2.4 times improvement in maximum speed over the conventional up/down counter [1]. After the ADC, the digital output of the sensor is ready to be readout. The column-parallel gain amplifier is implemented using a folded-cascode architecture at 3.3 V power supply. The specifications and simulated performance of the column-parallel gain amplifier are summarized in Table I. Fig. 2 shows the readout timing diagram of the pixel and column readout chain. Initially, the floating diffusion (FD) node of the pixel is reset, and then the column gain amplifier and the comparator are reset sequentially as well. The pixel reset transistor (RT), the amplifier reset switch Top, and the comparator reset switch Taz are closed sequentially. This sequential closing of the reset switches produces a “cascaded noise cancelling” process [2] which isolates the reset noise and offset noise of every previous stage by storing it in a subsequent capacitor and thus be cancelled by the analog correlated double sampling (CDS) later on [2], [3]. The digital CMS sequence is as follows. After the FD node is reset, the reset level is compared with the ramp voltage Vramp and the BWI counter is set to synchronously count up. When Vramp is equal to the reset level, the comparator output toggles from digital “high” to digital “low” and this stops the BWI counter from counting. The BWI counter value directly corresponds to the reset level in the column. For m-times sampling of the reset level, the reference ramp voltage Vramp for the comparator will be up and down ramping for m-times while the BWI counter will count m-times up. The latched counter output thus corresponds to m-times sampling of the reset level available on the column. After the signal charge transferred to the FD node, VC as the input voltage of the comparator goes up to the amplified signal level voltage accordingly. P9